module top(
	   output	    sdram_clk,
	   output	    sdram_cke,
	   output	    sdram_csn,
	   output	    sdram_wen,
	   output	    sdram_rasn,
	   output	    sdram_casn,
	   output [12:0]    sdram_a,
	   output [1:0]	    sdram_ba,
	   output [1:0]	    sdram_dqm,
	   inout [15:0]	    sdram_d,
	   
	   input	    clk_25mhz,
	   input [6:0]	    btn,
	   input [3:0]	    sw,
	   output [7:0] led,
	   output	    wifi_gpio0
	   );

   reg [25:0] addr = 0;
   reg [31:0] counter = 0;
   wire [31:0] data;
   wire	      wr, rd, clk_40mhz, rst;
   
   Clock1 _clk1(
		.clkin(clk_25mhz),
		.clkout0(clk_40mhz),
		.locked()
		);
   SDRAM _sdram(
		.sd_clk(sdram_clk),
		.sd_cke(sdram_cke),
		.sd_d(sdram_d),
		.sd_addr(sdram_a),
		.sd_ba(sdram_ba),
		.sd_dqm(sdram_dqm),
		.sd_cs(sdram_csn),
		.sd_we(sdram_wen),
		.sd_ras(sdram_rasn),
		.sd_cas(sdram_casn),
	       
		.clk(clk_40mhz),
		.resetn(!rst),
		.wmask(wr ? 4'b0001 : 4'b0),
		.rd(rd),
		.addr(addr),
		.din(counter),
		.dout(data),
		.busy(led[7])
		);

   wire change_counter = btn[3] || btn[4];
   wire	change_addr = btn[5] || btn[6];

   wire [31:0] next_counter = btn[3] ? counter + 1 : counter - 1;
   wire [25:0] next_addr = btn[5] ? addr - 4 : addr + 4;
   
   always@ (posedge change_counter or posedge rst)
      if (rst)
	counter <= 0;
      else
	counter <= next_counter;

   always@ (posedge change_addr or posedge rst)
     if (rst)
       addr <= 0;
     else
       addr <= next_addr;

   assign rd = btn[1];
   assign wr = btn[2];
   assign rst = ~btn[0];
   assign led[6:0] = data[6:0];
endmodule