module ClockDivider(
		    input  rst,
		    input  clk_in,
		    output clk_out
	      );

   reg clk = 0;
   reg [31:0] counter = 0;

   always@ (posedge clk_in or posedge rst)
     begin
	if (rst)
	  begin
	     counter <= 0;
	     clk <= 0;
	  end
	else if (counter == 32'd1_000_000)
	  begin
	     counter <= 0;
	     clk <= ~clk;
	  end
	else
	  counter <= counter + 1;
   end

   assign clk_out = ~clk;
endmodule

module top(
	   output	    sdram_clk,
	   output	    sdram_cke,
	   output	    sdram_csn,
	   output	    sdram_wen,
	   output	    sdram_rasn,
	   output	    sdram_casn,
	   output [12:0]    sdram_a,
	   output [1:0]	    sdram_ba,
	   output [1:0]	    sdram_dqm,
	   inout [15:0]	    sdram_d,
	   
	   input	    clk_25mhz,
	   input [6:0]	    btn,
	   input [3:0]	    sw,
	   output reg [7:0] led,
	   output	    wifi_gpio0
);

   wire [15:0] mem_addr, mem_data;
   wire	       mem_wr, mem_en, mem_busy;
   wire	       clk_40mhz, clk, rst;
   wire	       sdram;
   wire [31:0] sdram_dout;
   reg [15:0]  data;

   wire [15:0] irom [15:0];
   reg [15:0]  ram [127:0];

   Clock1 _clk1(
		  .clkin(clk_25mhz),
		  .clkout0(clk_40mhz),
		  .locked()
		  );

   ClockDivider _clk(
		     .clk_in(clk_40mhz),
		     .clk_out(clk),
		     .rst(rst)
		     );

   Processor _cpu(
		  .debug(),
		  .mem_addr(mem_addr),
		  .mem_data(mem_data),
		  .mem_wr(mem_wr),
		  .mem_en(mem_en),
		  .mem_busy(mem_busy),
		  .clk(clk),
		  .rst(rst)
		  );

   SDRAM _sdram(
		.sd_clk(sdram_clk),
		.sd_cke(sdram_cke),
		.sd_d(sdram_d),
		.sd_addr(sdram_a),
		.sd_ba(sdram_ba),
		.sd_dqm(sdram_dqm),
		.sd_cs(sdram_csn),
		.sd_we(sdram_wen),
		.sd_ras(sdram_rasn),
		.sd_cas(sdram_casn),
	       
		.clk(clk_40mhz),
		.resetn(!rst),
		.wmask(sdram && mem_wr ? 4'b0011 : 4'b0000),
		.rd(sdram && mem_en),
		.addr({ 18'b0, (mem_addr[7:0] << 1) }),
		.din({ 16'b0, mem_data }),
		.dout(sdram_dout),
		.busy(mem_busy)
		);
   

   always@ (posedge clk)
      if (mem_wr && !mem_en)
	case (mem_addr[15:8])
	  8'h10: ram[mem_addr[7:1]] <= mem_data;
	  8'h80: led <= mem_data[7:0];
	endcase

   always@ (*) begin
      case (mem_addr[15:8])
	8'h00: data <= irom[mem_addr[4:1]];
	8'h10: data <= ram[mem_addr[8:1]];
	default: data <= 16'hFFFF;
      endcase
   end

   assign sdram = mem_addr[15:8] == 8'h20;

   assign irom[4'h0] = 16'h3180; // 	lui r1, 0x80
   assign irom[4'h1] = 16'h3220; // 	lui r2, 0x20
   assign irom[4'h2] = 16'h4302; // l:	lw r3, [r2]
   assign irom[4'h3] = 16'h8031; // 	sw r3, [r1, 0]
   assign irom[4'h4] = 16'h2301; // 	addi r3, 1
   assign irom[4'h5] = 16'h8032; // 	sw r3, [r2, 0]
   assign irom[4'h6] = 16'hfffb; // 	j l
   assign irom[4'h7] = 16'hffff; //
   assign irom[4'h8] = 16'hffff; //
   assign irom[4'h9] = 16'hffff; //
   assign irom[4'hA] = 16'hffff; //
   assign irom[4'hB] = 16'hffff;
   assign irom[4'hC] = 16'hffff;
   assign irom[4'hD] = 16'hffff;
   assign irom[4'hE] = 16'hffff;
   assign irom[4'hF] = 16'hffff;

   assign wifi_gpio0 = clk;
   assign mem_data = mem_en && !mem_wr ? (sdram ? sdram_dout[15:0] : data) : 16'bz;
   assign rst = btn[2];
endmodule