1 // diamond 3.7 accepts this PLL
2 // diamond 3.8-3.9 is untested
3 // diamond 3.10 or higher is likely to abort with error about unable to use feedback signal
4 // cause of this could be from wrong CPHASE/FPHASE parameters
7 input clkin, // 25 MHz, 0 deg
8 output clkout0, // 40 MHz, 0 deg
11 (* FREQUENCY_PIN_CLKI="25" *)
12 (* FREQUENCY_PIN_CLKOP="40" *)
13 (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
15 .PLLRST_ENA("DISABLED"),
16 .INTFB_WAKE("DISABLED"),
17 .STDBY_ENABLE("DISABLED"),
18 .DPHASE_SOURCE("DISABLED"),
19 .OUTDIVIDER_MUXA("DIVA"),
20 .OUTDIVIDER_MUXB("DIVB"),
21 .OUTDIVIDER_MUXC("DIVC"),
22 .OUTDIVIDER_MUXD("DIVD"),
24 .CLKOP_ENABLE("ENABLED"),
28 .FEEDBK_PATH("CLKOP"),