2 // SDRAM interface to AS4C32M16SB-7TCN
3 // 512 Mbit Single-Data-Rate SDRAM, 32Mx16 (8M x 16 x 4 Banks)
5 // Matthias Koch, January 2022
7 // With a lot of inspiration from Mike Field, Hamsterworks:
9 // https://web.archive.org/web/20190215130043/http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller
10 // https://web.archive.org/web/20190215130043/http://hamsterworks.co.nz/mediawiki/index.php/File:Verilog_Memory_controller_v0.1.zip
12 // Note: You may need to change all values marked with *** when changing clock frequency. This is for 40 MHz.
16 // Interface to SDRAM chip, fully registered
18 output sd_clk, // Clock for SDRAM chip
19 output reg sd_cke, // Clock enabled
20 inout [15:0] sd_d, // Bidirectional data lines to/from SDRAM
21 output reg [12:0] sd_addr, // Address bus, multiplexed, 13 bits
22 output reg [1:0] sd_ba, // Bank select wires for 4 banks
23 output reg [1:0] sd_dqm, // Byte mask
24 output reg sd_cs, // Chip select
25 output reg sd_we, // Write enable
26 output reg sd_ras, // Row address select
27 output reg sd_cas, // Columns address select
29 // Interface to processor
37 output reg [31:0] dout,
41 parameter sdram_startup_cycles = 10100; // *** -- 100us, plus a little more, @ 100MHz
42 parameter sdram_refresh_cycles = 195; // *** The refresh operation must be performed 8192 times within 64ms. --> One refresh every 7.8125 us.
43 // With a minimum clock of 25 MHz, this results in one refresh every 7.8125e-6 * 25e6 = 195 cycles.
45 // ----------------------------------------------------------
46 // -- Connections and buffer primitives
47 // ----------------------------------------------------------
49 assign sd_clk = ~clk; // Supply memory chip with a clock.
51 wire [15:0] sd_data_in; // Bidirectional data from SDRAM
52 reg [15:0] sd_data_out; // Bidirectional data to SDRAM
53 reg sd_data_drive; // High: FPGA controls wires Low: SDRAM controls wires
58 reg [15:0] sd_data_in_buffered;
59 assign sd_d = sd_data_drive ? sd_data_out : 16'bz;
60 always @(posedge clk) sd_data_in_buffered <= sd_d;
61 assign sd_data_in = sd_data_in_buffered;
65 wire [15:0] sd_data_in_unbuffered; // To connect primitives internally
67 TRELLIS_IO #(.DIR("BIDIR"))
71 .O(sd_data_in_unbuffered),
75 // Registering the input is important for stability and delays data arrival by one clock cycle.
76 IFS1P3BX dbi_ff[15:0] (.D(sd_data_in_unbuffered), .Q(sd_data_in), .SCLK(clk), .PD({16{sd_data_drive}}));
79 // ----------------------------------------------------------
80 // -- Configuration to initialise the SDRAM chip
81 // ----------------------------------------------------------
83 // Taken from https://github.com/rxrbln/picorv32/blob/master/picosoc/sdram.v
85 localparam NO_WRITE_BURST = 1'b0; // 0=write burst enabled, 1=only single access write
86 localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
87 localparam CAS_LATENCY = 3'd2; // 2 or 3 cycles allowed
88 localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
89 localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
91 localparam MODE = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
93 // ----------------------------------------------------------
94 // -- All possible commands for the SDRAM chip
95 // ----------------------------------------------------------
98 localparam CMD_INHIBIT = 4'b1111;
100 localparam CMD_NOP = 4'b0111;
101 localparam CMD_BURST_TERMINATE = 4'b0110;
102 localparam CMD_READ = 4'b0101;
103 localparam CMD_WRITE = 4'b0100;
104 localparam CMD_ACTIVE = 4'b0011;
105 localparam CMD_PRECHARGE = 4'b0010;
106 localparam CMD_AUTO_REFRESH = 4'b0001;
107 localparam CMD_LOAD_MODE = 4'b0000;
109 // ----------------------------------------------------------
110 // -- States of the SDRAM controller
111 // ----------------------------------------------------------
113 localparam s_init_bit = 0; localparam s_init = 1 << s_init_bit ;
114 localparam s_idle_bit = 1; localparam s_idle = 1 << s_idle_bit ;
115 localparam s_activate_bit = 2; localparam s_activate = 1 << s_activate_bit ;
116 localparam s_read_1_bit = 3; localparam s_read_1 = 1 << s_read_1_bit ;
117 localparam s_read_2_bit = 4; localparam s_read_2 = 1 << s_read_2_bit ;
118 localparam s_read_3_bit = 5; localparam s_read_3 = 1 << s_read_3_bit ;
119 localparam s_read_4_bit = 6; localparam s_read_4 = 1 << s_read_4_bit ;
120 localparam s_read_5_bit = 7; localparam s_read_5 = 1 << s_read_5_bit ;
121 localparam s_write_1_bit = 8; localparam s_write_1 = 1 << s_write_1_bit ;
122 localparam s_write_2_bit = 9; localparam s_write_2 = 1 << s_write_2_bit ;
124 localparam s_idle_in_6_bit = 10; localparam s_idle_in_6 = 1 << s_idle_in_6_bit ;
125 localparam s_idle_in_5_bit = 11; localparam s_idle_in_5 = 1 << s_idle_in_5_bit ;
126 localparam s_idle_in_4_bit = 12; localparam s_idle_in_4 = 1 << s_idle_in_4_bit ;
127 localparam s_idle_in_3_bit = 13; localparam s_idle_in_3 = 1 << s_idle_in_3_bit ;
128 localparam s_idle_in_2_bit = 14; localparam s_idle_in_2 = 1 << s_idle_in_2_bit ;
129 localparam s_idle_in_1_bit = 15; localparam s_idle_in_1 = 1 << s_idle_in_1_bit ;
132 reg [15:0] state = s_init;
134 // ----------------------------------------------------------
135 // -- Access control wires
136 // ----------------------------------------------------------
138 reg [14:0] reset_counter = sdram_startup_cycles;
139 reg [7:0] refresh_counter = 0;
140 reg refresh_pending = 1;
142 reg [3:0] wmask_sticky = 4'b0000;
144 wire stillatwork = ~(state[s_read_5_bit] | state[s_write_2_bit]);
145 wire [8:0] refresh_counterN = refresh_counter - 1;
147 // ----------------------------------------------------------
148 // -- The memory controller
149 // ----------------------------------------------------------
151 always @(posedge clk)
154 reset_counter <= sdram_startup_cycles; // Counts backwards to zero
155 busy <= 0; // Technically, we are busy with initialisation, but there are no ongoing read or write requests
157 wmask_sticky <= 4'b0000;
161 // FemtoRV32 pulses read and write lines high for exactly one clock cycle.
162 // Address and data lines keep stable until busy is released.
163 // Therefore: Take note of the requested read or write, and assert busy flag immediately.
165 busy <= ((|wmask) | rd) | (busy & stillatwork );
166 rd_sticky <= rd | (rd_sticky & stillatwork );
167 wmask_sticky <= wmask | (wmask_sticky & {4{stillatwork}} );
169 // Schedule refreshes regularly
170 refresh_counter <= refresh_counterN[8] ? sdram_refresh_cycles : refresh_counterN[7:0];
171 refresh_pending <= (refresh_pending & ~state[s_idle_bit]) | refresh_counterN[8];
176 // Processor can already request the first read or write here, but has to wait then:
178 state[s_init_bit]: begin
180 //------------------------------------------------------------------------
181 //-- This is the initial startup state, where we wait for at least 100us
182 //-- before starting the start sequence
184 //-- The initialisation is sequence is
185 //-- * de-assert SDRAM_CKE
187 //-- * assert SDRAM_CKE
188 //-- * wait at least one cycle,
197 //------------------------------------------------------------------------
199 sd_ba <= 2'b00; // Reserved for future use in mode configuration
200 sd_dqm <= 2'b11; // Data bus in High-Z state
201 sd_data_drive <= 0; // Do not drive the data bus now
203 case (reset_counter) // Counts from a large value down to zero
205 33: begin sd_cke <= 1; end
207 // Ensure all rows are closed
208 31: begin {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_PRECHARGE; sd_addr <= 13'b0010000000000; end
210 // These refreshes need to be at least tRFC (63ns) apart
211 23: begin {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_AUTO_REFRESH; end
212 15: begin {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_AUTO_REFRESH; end
214 // Now load the mode register
215 7: begin {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_LOAD_MODE; sd_addr <= MODE; end
217 default: {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_NOP;
220 reset_counter <= reset_counter - 1;
221 if (reset_counter == 0) state <= s_idle;
224 // New read or write requests from the processor may arrive in these states:
226 //-----------------------------------------------------
227 //-- Additional NOPs to meet timing requirements
228 //-----------------------------------------------------
230 state[s_idle_in_6_bit]: begin state <= s_idle_in_5; {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_NOP; end
231 state[s_idle_in_5_bit]: begin state <= s_idle_in_4; {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_NOP; end
232 state[s_idle_in_4_bit]: begin state <= s_idle_in_3; {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_NOP; end
233 state[s_idle_in_3_bit]: begin state <= s_idle_in_2; {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_NOP; end
234 state[s_idle_in_2_bit]: begin state <= s_idle_in_1; {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_NOP; end
235 state[s_idle_in_1_bit]: begin state <= s_idle; {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_NOP; end
237 // Refresh cycle needs tRFC (63ns), so 6 idle cycles are needed @ 100MHz
239 //-----------------------------------------------------
240 //-- Dispatch all possible actions while idling (NOP)
241 //-----------------------------------------------------
243 state[s_idle_bit]: begin
244 sd_ba <= addr[23:22]; // Bank select, 2 bits
245 sd_addr <= {addr[25:24], addr[21:11]} ; // RA0-RA12: 8192 Row address
247 {sd_cs, sd_ras, sd_cas, sd_we} <= refresh_pending ? CMD_AUTO_REFRESH :
248 (|wmask_sticky) | rd_sticky ? CMD_ACTIVE :
251 state <= refresh_pending ? s_idle_in_2 : // *** Experimental result: Direct transition to s_idle does not work @ 40 MHz, s_idle_in_1 is unstable, sd_idle_in_2 is fine.
252 (|wmask_sticky) | rd_sticky ? s_activate :
256 // Busy flag is set while state machine is in the following states:
258 //-----------------------------------------------------
259 //-- Opening the row ready for reads or writes
260 //-----------------------------------------------------
262 state[s_activate_bit]: begin
263 sd_data_drive <= ~rd_sticky; // Drive or release bus early, before the SDRAM chip takes over to drive these lines
264 {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_NOP;
265 state <= rd_sticky ? s_read_1 : s_write_1;
268 // RAS-to-CAS delay, also necessary for precharge, used in this state machine: 2 cycles.
269 // Specification of AS4C32M16SB-7TCN: 21 ns --> Good for 1/(21e-9 / 2) = 95.23 MHz
271 //-----------------------------------------------------
272 //-- Processing the read transaction
273 //-----------------------------------------------------
275 state[s_read_1_bit]: begin
276 sd_dqm <= 2'b00; // SDRAM chip shall drive the bus lines
277 {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_READ;
278 sd_addr <= {3'b001, addr[10:2], 1'b0}; // Bit 10: Auto-precharge. CA0-CA9: 1024 Column address.
282 state[s_read_2_bit]: begin
283 {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_NOP;
287 state[s_read_3_bit]: state <= s_read_4;
290 state[s_read_4_bit]: begin
291 dout[15:0] <= sd_data_in;
295 // Busy is cleared when reaching this state, fulfilling the request:
297 state[s_read_5_bit]: begin
298 dout[31:16] <= sd_data_in;
299 state <= s_idle; // *** Experimental result: Direct transition to s_idle is fine @ 40 MHz
302 // Precharge (which is automatic here) needs 21 ns, therefore 2 idle cycles need to be inserted
304 //-----------------------------------------------------
305 // -- Processing the write transaction
306 //-----------------------------------------------------
308 state[s_write_1_bit]: begin
309 sd_addr <= {3'b001, addr[10:2], 1'b0}; // Bit 10: Auto-precharge. CA0-CA9: 1024 Column address.
310 sd_data_out <= din[15:0];
311 sd_dqm <= ~wmask_sticky[1:0];
312 {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_WRITE;
316 // Busy is cleared when reaching this state, fulfilling the request:
318 state[s_write_2_bit]: begin
319 sd_data_out <= din[31:16];
320 sd_dqm <= ~wmask_sticky[3:2];
321 {sd_cs, sd_ras, sd_cas, sd_we} <= CMD_NOP;
322 state <= s_idle_in_2; // *** Experimental result: s_idle_in_1 does not work @ 40 MHz, s_idle_in_2 is fine.
325 // Write needs 14 ns internally, then Precharge needs 21 ns, therefore 3 idle cycles need to be inserted
