1 8515162d 2024-02-02 benni // diamond 3.7 accepts this PLL
 2 8515162d 2024-02-02 benni // diamond 3.8-3.9 is untested
 3 8515162d 2024-02-02 benni // diamond 3.10 or higher is likely to abort with error about unable to use feedback signal
 4 8515162d 2024-02-02 benni // cause of this could be from wrong CPHASE/FPHASE parameters
 5 8515162d 2024-02-02 benni module Clock1
 6 8515162d 2024-02-02 benni (
 7 8515162d 2024-02-02 benni     input clkin, // 25 MHz, 0 deg
 8 8515162d 2024-02-02 benni     output clkout0, // 40 MHz, 0 deg
 9 8515162d 2024-02-02 benni     output locked
10 8515162d 2024-02-02 benni );
11 8515162d 2024-02-02 benni (* FREQUENCY_PIN_CLKI="25" *)
12 8515162d 2024-02-02 benni (* FREQUENCY_PIN_CLKOP="40" *)
13 8515162d 2024-02-02 benni (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
14 8515162d 2024-02-02 benni EHXPLLL #(
15 8515162d 2024-02-02 benni         .PLLRST_ENA("DISABLED"),
16 8515162d 2024-02-02 benni         .INTFB_WAKE("DISABLED"),
17 8515162d 2024-02-02 benni         .STDBY_ENABLE("DISABLED"),
18 8515162d 2024-02-02 benni         .DPHASE_SOURCE("DISABLED"),
19 8515162d 2024-02-02 benni         .OUTDIVIDER_MUXA("DIVA"),
20 8515162d 2024-02-02 benni         .OUTDIVIDER_MUXB("DIVB"),
21 8515162d 2024-02-02 benni         .OUTDIVIDER_MUXC("DIVC"),
22 8515162d 2024-02-02 benni         .OUTDIVIDER_MUXD("DIVD"),
23 8515162d 2024-02-02 benni         .CLKI_DIV(5),
24 8515162d 2024-02-02 benni         .CLKOP_ENABLE("ENABLED"),
25 8515162d 2024-02-02 benni         .CLKOP_DIV(15),
26 8515162d 2024-02-02 benni         .CLKOP_CPHASE(7),
27 8515162d 2024-02-02 benni         .CLKOP_FPHASE(0),
28 8515162d 2024-02-02 benni         .FEEDBK_PATH("CLKOP"),
29 8515162d 2024-02-02 benni         .CLKFB_DIV(8)
30 8515162d 2024-02-02 benni     ) pll_i (
31 8515162d 2024-02-02 benni         .RST(1'b0),
32 8515162d 2024-02-02 benni         .STDBY(1'b0),
33 8515162d 2024-02-02 benni         .CLKI(clkin),
34 8515162d 2024-02-02 benni         .CLKOP(clkout0),
35 8515162d 2024-02-02 benni         .CLKFB(clkout0),
36 8515162d 2024-02-02 benni         .CLKINTFB(),
37 8515162d 2024-02-02 benni         .PHASESEL0(1'b0),
38 8515162d 2024-02-02 benni         .PHASESEL1(1'b0),
39 8515162d 2024-02-02 benni         .PHASEDIR(1'b1),
40 8515162d 2024-02-02 benni         .PHASESTEP(1'b1),
41 8515162d 2024-02-02 benni         .PHASELOADREG(1'b1),
42 8515162d 2024-02-02 benni         .PLLWAKESYNC(1'b0),
43 8515162d 2024-02-02 benni         .ENCLKOP(1'b0),
44 8515162d 2024-02-02 benni         .LOCK(locked)
45 8515162d 2024-02-02 benni 	);
46 8515162d 2024-02-02 benni endmodule