1 // diamond 3.7 accepts this PLL
2 // diamond 3.8-3.9 is untested
3 // diamond 3.10 or higher is likely to abort with error about unable to use feedback signal
4 // cause of this could be from wrong CPHASE/FPHASE parameters
5 module Clock1
6 (
7     input clkin, // 25 MHz, 0 deg
8     output clkout0, // 40 MHz, 0 deg
9     output locked
10 );
11 (* FREQUENCY_PIN_CLKI="25" *)
12 (* FREQUENCY_PIN_CLKOP="40" *)
13 (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
14 EHXPLLL #(
15         .PLLRST_ENA("DISABLED"),
16         .INTFB_WAKE("DISABLED"),
17         .STDBY_ENABLE("DISABLED"),
18         .DPHASE_SOURCE("DISABLED"),
19         .OUTDIVIDER_MUXA("DIVA"),
20         .OUTDIVIDER_MUXB("DIVB"),
21         .OUTDIVIDER_MUXC("DIVC"),
22         .OUTDIVIDER_MUXD("DIVD"),
23         .CLKI_DIV(5),
24         .CLKOP_ENABLE("ENABLED"),
25         .CLKOP_DIV(15),
26         .CLKOP_CPHASE(7),
27         .CLKOP_FPHASE(0),
28         .FEEDBK_PATH("CLKOP"),
29         .CLKFB_DIV(8)
30     ) pll_i (
31         .RST(1'b0),
32         .STDBY(1'b0),
33         .CLKI(clkin),
34         .CLKOP(clkout0),
35         .CLKFB(clkout0),
36         .CLKINTFB(),
37         .PHASESEL0(1'b0),
38         .PHASESEL1(1'b0),
39         .PHASEDIR(1'b1),
40         .PHASESTEP(1'b1),
41         .PHASELOADREG(1'b1),
42         .PLLWAKESYNC(1'b0),
43         .ENCLKOP(1'b0),
44         .LOCK(locked)
45 	);
46 endmodule