1 8515162d 2024-02-02 benni 
 2 8515162d 2024-02-02 benni module top(
 3 8515162d 2024-02-02 benni 	   output	    sdram_clk,
 4 8515162d 2024-02-02 benni 	   output	    sdram_cke,
 5 8515162d 2024-02-02 benni 	   output	    sdram_csn,
 6 8515162d 2024-02-02 benni 	   output	    sdram_wen,
 7 8515162d 2024-02-02 benni 	   output	    sdram_rasn,
 8 8515162d 2024-02-02 benni 	   output	    sdram_casn,
 9 8515162d 2024-02-02 benni 	   output [12:0]    sdram_a,
10 8515162d 2024-02-02 benni 	   output [1:0]	    sdram_ba,
11 8515162d 2024-02-02 benni 	   output [1:0]	    sdram_dqm,
12 8515162d 2024-02-02 benni 	   inout [15:0]	    sdram_d,
13 8515162d 2024-02-02 benni 	   
14 8515162d 2024-02-02 benni 	   input	    clk_25mhz,
15 8515162d 2024-02-02 benni 	   input [6:0]	    btn,
16 8515162d 2024-02-02 benni 	   input [3:0]	    sw,
17 8515162d 2024-02-02 benni 	   output [7:0] led,
18 8515162d 2024-02-02 benni 	   output	    wifi_gpio0
19 8515162d 2024-02-02 benni 	   );
20 8515162d 2024-02-02 benni 
21 8515162d 2024-02-02 benni    reg [25:0] addr = 0;
22 8515162d 2024-02-02 benni    reg [31:0] counter = 0;
23 8515162d 2024-02-02 benni    wire [31:0] data;
24 8515162d 2024-02-02 benni    wire	      wr, rd, clk_40mhz, rst;
25 8515162d 2024-02-02 benni    
26 8515162d 2024-02-02 benni    Clock1 _clk1(
27 8515162d 2024-02-02 benni 		.clkin(clk_25mhz),
28 8515162d 2024-02-02 benni 		.clkout0(clk_40mhz),
29 8515162d 2024-02-02 benni 		.locked()
30 8515162d 2024-02-02 benni 		);
31 8515162d 2024-02-02 benni    SDRAM _sdram(
32 8515162d 2024-02-02 benni 		.sd_clk(sdram_clk),
33 8515162d 2024-02-02 benni 		.sd_cke(sdram_cke),
34 8515162d 2024-02-02 benni 		.sd_d(sdram_d),
35 8515162d 2024-02-02 benni 		.sd_addr(sdram_a),
36 8515162d 2024-02-02 benni 		.sd_ba(sdram_ba),
37 8515162d 2024-02-02 benni 		.sd_dqm(sdram_dqm),
38 8515162d 2024-02-02 benni 		.sd_cs(sdram_csn),
39 8515162d 2024-02-02 benni 		.sd_we(sdram_wen),
40 8515162d 2024-02-02 benni 		.sd_ras(sdram_rasn),
41 8515162d 2024-02-02 benni 		.sd_cas(sdram_casn),
42 8515162d 2024-02-02 benni 	       
43 8515162d 2024-02-02 benni 		.clk(clk_40mhz),
44 8515162d 2024-02-02 benni 		.resetn(!rst),
45 8515162d 2024-02-02 benni 		.wmask(wr ? 4'b0001 : 4'b0),
46 8515162d 2024-02-02 benni 		.rd(rd),
47 8515162d 2024-02-02 benni 		.addr(addr),
48 8515162d 2024-02-02 benni 		.din(counter),
49 8515162d 2024-02-02 benni 		.dout(data),
50 8515162d 2024-02-02 benni 		.busy(led[7])
51 8515162d 2024-02-02 benni 		);
52 8515162d 2024-02-02 benni 
53 8515162d 2024-02-02 benni    wire change_counter = btn[3] || btn[4];
54 8515162d 2024-02-02 benni    wire	change_addr = btn[5] || btn[6];
55 8515162d 2024-02-02 benni 
56 8515162d 2024-02-02 benni    wire [31:0] next_counter = btn[3] ? counter + 1 : counter - 1;
57 8515162d 2024-02-02 benni    wire [25:0] next_addr = btn[5] ? addr - 4 : addr + 4;
58 8515162d 2024-02-02 benni    
59 8515162d 2024-02-02 benni    always@ (posedge change_counter or posedge rst)
60 8515162d 2024-02-02 benni       if (rst)
61 8515162d 2024-02-02 benni 	counter <= 0;
62 8515162d 2024-02-02 benni       else
63 8515162d 2024-02-02 benni 	counter <= next_counter;
64 8515162d 2024-02-02 benni 
65 8515162d 2024-02-02 benni    always@ (posedge change_addr or posedge rst)
66 8515162d 2024-02-02 benni      if (rst)
67 8515162d 2024-02-02 benni        addr <= 0;
68 8515162d 2024-02-02 benni      else
69 8515162d 2024-02-02 benni        addr <= next_addr;
70 8515162d 2024-02-02 benni 
71 8515162d 2024-02-02 benni    assign rd = btn[1];
72 8515162d 2024-02-02 benni    assign wr = btn[2];
73 8515162d 2024-02-02 benni    assign rst = ~btn[0];
74 8515162d 2024-02-02 benni    assign led[6:0] = data[6:0];
75 8515162d 2024-02-02 benni endmodule