1 
2 module top(
3 	   output	    sdram_clk,
4 	   output	    sdram_cke,
5 	   output	    sdram_csn,
6 	   output	    sdram_wen,
7 	   output	    sdram_rasn,
8 	   output	    sdram_casn,
9 	   output [12:0]    sdram_a,
10 	   output [1:0]	    sdram_ba,
11 	   output [1:0]	    sdram_dqm,
12 	   inout [15:0]	    sdram_d,
13 	   
14 	   input	    clk_25mhz,
15 	   input [6:0]	    btn,
16 	   input [3:0]	    sw,
17 	   output [7:0] led,
18 	   output	    wifi_gpio0
19 	   );
20 
21    reg [25:0] addr = 0;
22    reg [31:0] counter = 0;
23    wire [31:0] data;
24    wire	      wr, rd, clk_40mhz, rst;
25    
26    Clock1 _clk1(
27 		.clkin(clk_25mhz),
28 		.clkout0(clk_40mhz),
29 		.locked()
30 		);
31    SDRAM _sdram(
32 		.sd_clk(sdram_clk),
33 		.sd_cke(sdram_cke),
34 		.sd_d(sdram_d),
35 		.sd_addr(sdram_a),
36 		.sd_ba(sdram_ba),
37 		.sd_dqm(sdram_dqm),
38 		.sd_cs(sdram_csn),
39 		.sd_we(sdram_wen),
40 		.sd_ras(sdram_rasn),
41 		.sd_cas(sdram_casn),
42 	       
43 		.clk(clk_40mhz),
44 		.resetn(!rst),
45 		.wmask(wr ? 4'b0001 : 4'b0),
46 		.rd(rd),
47 		.addr(addr),
48 		.din(counter),
49 		.dout(data),
50 		.busy(led[7])
51 		);
52 
53    wire change_counter = btn[3] || btn[4];
54    wire	change_addr = btn[5] || btn[6];
55 
56    wire [31:0] next_counter = btn[3] ? counter + 1 : counter - 1;
57    wire [25:0] next_addr = btn[5] ? addr - 4 : addr + 4;
58    
59    always@ (posedge change_counter or posedge rst)
60       if (rst)
61 	counter <= 0;
62       else
63 	counter <= next_counter;
64 
65    always@ (posedge change_addr or posedge rst)
66      if (rst)
67        addr <= 0;
68      else
69        addr <= next_addr;
70 
71    assign rd = btn[1];
72    assign wr = btn[2];
73    assign rst = ~btn[0];
74    assign led[6:0] = data[6:0];
75 endmodule