1 8515162d 2024-02-02 benni module ClockDivider(
  2 8515162d 2024-02-02 benni 		    input  rst,
  3 8515162d 2024-02-02 benni 		    input  clk_in,
  4 8515162d 2024-02-02 benni 		    output clk_out
  5 8515162d 2024-02-02 benni 	      );
  6 8515162d 2024-02-02 benni 
  7 8515162d 2024-02-02 benni    reg clk = 0;
  8 8515162d 2024-02-02 benni    reg [31:0] counter = 0;
  9 8515162d 2024-02-02 benni 
 10 8515162d 2024-02-02 benni    always@ (posedge clk_in or posedge rst)
 11 8515162d 2024-02-02 benni      begin
 12 8515162d 2024-02-02 benni 	if (rst)
 13 8515162d 2024-02-02 benni 	  begin
 14 8515162d 2024-02-02 benni 	     counter <= 0;
 15 8515162d 2024-02-02 benni 	     clk <= 0;
 16 8515162d 2024-02-02 benni 	  end
 17 8515162d 2024-02-02 benni 	else if (counter == 32'd1_000_000)
 18 8515162d 2024-02-02 benni 	  begin
 19 8515162d 2024-02-02 benni 	     counter <= 0;
 20 8515162d 2024-02-02 benni 	     clk <= ~clk;
 21 8515162d 2024-02-02 benni 	  end
 22 8515162d 2024-02-02 benni 	else
 23 8515162d 2024-02-02 benni 	  counter <= counter + 1;
 24 8515162d 2024-02-02 benni    end
 25 8515162d 2024-02-02 benni 
 26 8515162d 2024-02-02 benni    assign clk_out = ~clk;
 27 8515162d 2024-02-02 benni endmodule
 28 8515162d 2024-02-02 benni 
 29 8515162d 2024-02-02 benni module top(
 30 8515162d 2024-02-02 benni 	   output	    sdram_clk,
 31 8515162d 2024-02-02 benni 	   output	    sdram_cke,
 32 8515162d 2024-02-02 benni 	   output	    sdram_csn,
 33 8515162d 2024-02-02 benni 	   output	    sdram_wen,
 34 8515162d 2024-02-02 benni 	   output	    sdram_rasn,
 35 8515162d 2024-02-02 benni 	   output	    sdram_casn,
 36 8515162d 2024-02-02 benni 	   output [12:0]    sdram_a,
 37 8515162d 2024-02-02 benni 	   output [1:0]	    sdram_ba,
 38 8515162d 2024-02-02 benni 	   output [1:0]	    sdram_dqm,
 39 8515162d 2024-02-02 benni 	   inout [15:0]	    sdram_d,
 40 8515162d 2024-02-02 benni 	   
 41 8515162d 2024-02-02 benni 	   input	    clk_25mhz,
 42 8515162d 2024-02-02 benni 	   input [6:0]	    btn,
 43 8515162d 2024-02-02 benni 	   input [3:0]	    sw,
 44 8515162d 2024-02-02 benni 	   output reg [7:0] led,
 45 8515162d 2024-02-02 benni 	   output	    wifi_gpio0
 46 8515162d 2024-02-02 benni );
 47 8515162d 2024-02-02 benni 
 48 8515162d 2024-02-02 benni    wire [15:0] mem_addr, mem_data;
 49 8515162d 2024-02-02 benni    wire	       mem_wr, mem_en, mem_busy;
 50 8515162d 2024-02-02 benni    wire	       clk_40mhz, clk, rst;
 51 8515162d 2024-02-02 benni    wire	       sdram;
 52 8515162d 2024-02-02 benni    wire [31:0] sdram_dout;
 53 8515162d 2024-02-02 benni    reg [15:0]  data;
 54 8515162d 2024-02-02 benni 
 55 8515162d 2024-02-02 benni    wire [15:0] irom [15:0];
 56 8515162d 2024-02-02 benni    reg [15:0]  ram [127:0];
 57 8515162d 2024-02-02 benni 
 58 8515162d 2024-02-02 benni    Clock1 _clk1(
 59 8515162d 2024-02-02 benni 		  .clkin(clk_25mhz),
 60 8515162d 2024-02-02 benni 		  .clkout0(clk_40mhz),
 61 8515162d 2024-02-02 benni 		  .locked()
 62 8515162d 2024-02-02 benni 		  );
 63 8515162d 2024-02-02 benni 
 64 8515162d 2024-02-02 benni    ClockDivider _clk(
 65 8515162d 2024-02-02 benni 		     .clk_in(clk_40mhz),
 66 8515162d 2024-02-02 benni 		     .clk_out(clk),
 67 8515162d 2024-02-02 benni 		     .rst(rst)
 68 8515162d 2024-02-02 benni 		     );
 69 8515162d 2024-02-02 benni 
 70 8515162d 2024-02-02 benni    Processor _cpu(
 71 8515162d 2024-02-02 benni 		  .debug(),
 72 8515162d 2024-02-02 benni 		  .mem_addr(mem_addr),
 73 8515162d 2024-02-02 benni 		  .mem_data(mem_data),
 74 8515162d 2024-02-02 benni 		  .mem_wr(mem_wr),
 75 8515162d 2024-02-02 benni 		  .mem_en(mem_en),
 76 8515162d 2024-02-02 benni 		  .mem_busy(mem_busy),
 77 8515162d 2024-02-02 benni 		  .clk(clk),
 78 8515162d 2024-02-02 benni 		  .rst(rst)
 79 8515162d 2024-02-02 benni 		  );
 80 8515162d 2024-02-02 benni 
 81 8515162d 2024-02-02 benni    SDRAM _sdram(
 82 8515162d 2024-02-02 benni 		.sd_clk(sdram_clk),
 83 8515162d 2024-02-02 benni 		.sd_cke(sdram_cke),
 84 8515162d 2024-02-02 benni 		.sd_d(sdram_d),
 85 8515162d 2024-02-02 benni 		.sd_addr(sdram_a),
 86 8515162d 2024-02-02 benni 		.sd_ba(sdram_ba),
 87 8515162d 2024-02-02 benni 		.sd_dqm(sdram_dqm),
 88 8515162d 2024-02-02 benni 		.sd_cs(sdram_csn),
 89 8515162d 2024-02-02 benni 		.sd_we(sdram_wen),
 90 8515162d 2024-02-02 benni 		.sd_ras(sdram_rasn),
 91 8515162d 2024-02-02 benni 		.sd_cas(sdram_casn),
 92 8515162d 2024-02-02 benni 	       
 93 8515162d 2024-02-02 benni 		.clk(clk_40mhz),
 94 8515162d 2024-02-02 benni 		.resetn(!rst),
 95 8515162d 2024-02-02 benni 		.wmask(sdram && mem_wr ? 4'b0011 : 4'b0000),
 96 8515162d 2024-02-02 benni 		.rd(sdram && mem_en),
 97 8515162d 2024-02-02 benni 		.addr({ 18'b0, (mem_addr[7:0] << 1) }),
 98 8515162d 2024-02-02 benni 		.din({ 16'b0, mem_data }),
 99 8515162d 2024-02-02 benni 		.dout(sdram_dout),
100 8515162d 2024-02-02 benni 		.busy(mem_busy)
101 8515162d 2024-02-02 benni 		);
102 8515162d 2024-02-02 benni    
103 8515162d 2024-02-02 benni 
104 8515162d 2024-02-02 benni    always@ (posedge clk)
105 8515162d 2024-02-02 benni       if (mem_wr && !mem_en)
106 8515162d 2024-02-02 benni 	case (mem_addr[15:8])
107 8515162d 2024-02-02 benni 	  8'h10: ram[mem_addr[7:1]] <= mem_data;
108 8515162d 2024-02-02 benni 	  8'h80: led <= mem_data[7:0];
109 8515162d 2024-02-02 benni 	endcase
110 8515162d 2024-02-02 benni 
111 8515162d 2024-02-02 benni    always@ (*) begin
112 8515162d 2024-02-02 benni       case (mem_addr[15:8])
113 8515162d 2024-02-02 benni 	8'h00: data <= irom[mem_addr[4:1]];
114 8515162d 2024-02-02 benni 	8'h10: data <= ram[mem_addr[8:1]];
115 8515162d 2024-02-02 benni 	default: data <= 16'hFFFF;
116 8515162d 2024-02-02 benni       endcase
117 8515162d 2024-02-02 benni    end
118 8515162d 2024-02-02 benni 
119 8515162d 2024-02-02 benni    assign sdram = mem_addr[15:8] == 8'h20;
120 8515162d 2024-02-02 benni 
121 8515162d 2024-02-02 benni    assign irom[4'h0] = 16'h3180; // 	lui r1, 0x80
122 8515162d 2024-02-02 benni    assign irom[4'h1] = 16'h3220; // 	lui r2, 0x20
123 8515162d 2024-02-02 benni    assign irom[4'h2] = 16'h4302; // l:	lw r3, [r2]
124 8515162d 2024-02-02 benni    assign irom[4'h3] = 16'h8031; // 	sw r3, [r1, 0]
125 8515162d 2024-02-02 benni    assign irom[4'h4] = 16'h2301; // 	addi r3, 1
126 8515162d 2024-02-02 benni    assign irom[4'h5] = 16'h8032; // 	sw r3, [r2, 0]
127 8515162d 2024-02-02 benni    assign irom[4'h6] = 16'hfffb; // 	j l
128 8515162d 2024-02-02 benni    assign irom[4'h7] = 16'hffff; //
129 8515162d 2024-02-02 benni    assign irom[4'h8] = 16'hffff; //
130 8515162d 2024-02-02 benni    assign irom[4'h9] = 16'hffff; //
131 8515162d 2024-02-02 benni    assign irom[4'hA] = 16'hffff; //
132 8515162d 2024-02-02 benni    assign irom[4'hB] = 16'hffff;
133 8515162d 2024-02-02 benni    assign irom[4'hC] = 16'hffff;
134 8515162d 2024-02-02 benni    assign irom[4'hD] = 16'hffff;
135 8515162d 2024-02-02 benni    assign irom[4'hE] = 16'hffff;
136 8515162d 2024-02-02 benni    assign irom[4'hF] = 16'hffff;
137 8515162d 2024-02-02 benni 
138 8515162d 2024-02-02 benni    assign wifi_gpio0 = clk;
139 8515162d 2024-02-02 benni    assign mem_data = mem_en && !mem_wr ? (sdram ? sdram_dout[15:0] : data) : 16'bz;
140 8515162d 2024-02-02 benni    assign rst = btn[2];
141 8515162d 2024-02-02 benni endmodule