1 module ClockDivider(
2 		    input  rst,
3 		    input  clk_in,
4 		    output clk_out
5 	      );
6 
7    reg clk = 0;
8    reg [31:0] counter = 0;
9 
10    always@ (posedge clk_in or posedge rst)
11      begin
12 	if (rst)
13 	  begin
14 	     counter <= 0;
15 	     clk <= 0;
16 	  end
17 	else if (counter == 32'd1_000_000)
18 	  begin
19 	     counter <= 0;
20 	     clk <= ~clk;
21 	  end
22 	else
23 	  counter <= counter + 1;
24    end
25 
26    assign clk_out = ~clk;
27 endmodule
28 
29 module top(
30 	   output	    sdram_clk,
31 	   output	    sdram_cke,
32 	   output	    sdram_csn,
33 	   output	    sdram_wen,
34 	   output	    sdram_rasn,
35 	   output	    sdram_casn,
36 	   output [12:0]    sdram_a,
37 	   output [1:0]	    sdram_ba,
38 	   output [1:0]	    sdram_dqm,
39 	   inout [15:0]	    sdram_d,
40 	   
41 	   input	    clk_25mhz,
42 	   input [6:0]	    btn,
43 	   input [3:0]	    sw,
44 	   output reg [7:0] led,
45 	   output	    wifi_gpio0
46 );
47 
48    wire [15:0] mem_addr, mem_data;
49    wire	       mem_wr, mem_en, mem_busy;
50    wire	       clk_40mhz, clk, rst;
51    wire	       sdram;
52    wire [31:0] sdram_dout;
53    reg [15:0]  data;
54 
55    wire [15:0] irom [15:0];
56    reg [15:0]  ram [127:0];
57 
58    Clock1 _clk1(
59 		  .clkin(clk_25mhz),
60 		  .clkout0(clk_40mhz),
61 		  .locked()
62 		  );
63 
64    ClockDivider _clk(
65 		     .clk_in(clk_40mhz),
66 		     .clk_out(clk),
67 		     .rst(rst)
68 		     );
69 
70    Processor _cpu(
71 		  .debug(),
72 		  .mem_addr(mem_addr),
73 		  .mem_data(mem_data),
74 		  .mem_wr(mem_wr),
75 		  .mem_en(mem_en),
76 		  .mem_busy(mem_busy),
77 		  .clk(clk),
78 		  .rst(rst)
79 		  );
80 
81    SDRAM _sdram(
82 		.sd_clk(sdram_clk),
83 		.sd_cke(sdram_cke),
84 		.sd_d(sdram_d),
85 		.sd_addr(sdram_a),
86 		.sd_ba(sdram_ba),
87 		.sd_dqm(sdram_dqm),
88 		.sd_cs(sdram_csn),
89 		.sd_we(sdram_wen),
90 		.sd_ras(sdram_rasn),
91 		.sd_cas(sdram_casn),
92 	       
93 		.clk(clk_40mhz),
94 		.resetn(!rst),
95 		.wmask(sdram && mem_wr ? 4'b0011 : 4'b0000),
96 		.rd(sdram && mem_en),
97 		.addr({ 18'b0, (mem_addr[7:0] << 1) }),
98 		.din({ 16'b0, mem_data }),
99 		.dout(sdram_dout),
100 		.busy(mem_busy)
101 		);
102    
103 
104    always@ (posedge clk)
105       if (mem_wr && !mem_en)
106 	case (mem_addr[15:8])
107 	  8'h10: ram[mem_addr[7:1]] <= mem_data;
108 	  8'h80: led <= mem_data[7:0];
109 	endcase
110 
111    always@ (*) begin
112       case (mem_addr[15:8])
113 	8'h00: data <= irom[mem_addr[4:1]];
114 	8'h10: data <= ram[mem_addr[8:1]];
115 	default: data <= 16'hFFFF;
116       endcase
117    end
118 
119    assign sdram = mem_addr[15:8] == 8'h20;
120 
121    assign irom[4'h0] = 16'h3180; // 	lui r1, 0x80
122    assign irom[4'h1] = 16'h3220; // 	lui r2, 0x20
123    assign irom[4'h2] = 16'h4302; // l:	lw r3, [r2]
124    assign irom[4'h3] = 16'h8031; // 	sw r3, [r1, 0]
125    assign irom[4'h4] = 16'h2301; // 	addi r3, 1
126    assign irom[4'h5] = 16'h8032; // 	sw r3, [r2, 0]
127    assign irom[4'h6] = 16'hfffb; // 	j l
128    assign irom[4'h7] = 16'hffff; //
129    assign irom[4'h8] = 16'hffff; //
130    assign irom[4'h9] = 16'hffff; //
131    assign irom[4'hA] = 16'hffff; //
132    assign irom[4'hB] = 16'hffff;
133    assign irom[4'hC] = 16'hffff;
134    assign irom[4'hD] = 16'hffff;
135    assign irom[4'hE] = 16'hffff;
136    assign irom[4'hF] = 16'hffff;
137 
138    assign wifi_gpio0 = clk;
139    assign mem_data = mem_en && !mem_wr ? (sdram ? sdram_dout[15:0] : data) : 16'bz;
140    assign rst = btn[2];
141 endmodule